The present invention relates, in general, to interconnect structures for semiconductor devices and, more particularly, to quantum well interconnect structures for semiconductor devices.
As semiconductor device dimensions approach the sub-micron level, one of the limiting factors for further reduction in size is area required for device interconnections. One possible solution is multilevel metallization in which two or more interconnect layers are formed on top of a device, separated by an inter-layer dielectric, and coupled by holes, or vias, which are filled with a via metallization. Even with multilayer metallization, though, the area required for vias limits further reduction in device size.
Small metal vias also result in current crowding and less reliable operation due to electromigration effects. Current crowding occurs at metal corners at the interface between the interconnect layer and the via metallization, resulting in higher current density at the corners than in the body of the via metallization. Current crowding effects significantly reduced the lifetime and reliability of the via metallization. These reliability problems are complicated in modern devices which require millions of metal interconnections.
Another problem with previous multilayer metallization processes was filling the via with the via metallization without creating voids so that a high quality electrical contact was formed. Conventional metal deposition methods such as evaporation, sputtering, and reactive ion sputtering have been used to fill vias. These metal deposition methods result in poor step coverage in small vias, which is aggravated as the aspect ratio, that is the ratio of height to width of the via, increased. Poor step coverage forces manufacturers to slope the via walls to step coverage and decrease the aspect ratio, but also increased the dimensions of the contact. What is needed is a truly compact, reliable interconnect method and structure that does not use conventional metal materials and processes.